1. Field of the Invention
This invention relates to electronic device fabrication and, more particularly, to device fabrication involving silicon.
2. Art Background
In most electronic components, such as integrated circuits, lateral separation is produced between regions of essentially single crystal silicon, i.e., silicon having less than a total of 10.sup.8 cm.sup.-2 defects, e.g., linear and planar defects such as dislocations or stacking faults, respectively. This separation is accomplished by interposing between the single crystal silicon regions a region of electrically insulating material having a thickness approximately equal to the depth of the active regions of the single crystal materials being separated. (The active region is that portion of the single crystal silicon which is modified to contain electronic device structures. The active region is typically 1 .mu.m thick for nominal voltage devices.) Alternatively, a p-n barrier separates the device regions. In this manner, transistors or other devices formed in one single crystal region, i.e., one active region, are electrically isolated and are prevented from interacting with devices in a second active region.
However, for some significant applications, the use of lateral isolation alone is not sufficient. For example, in some instances, the voltage employed in operation is often large enough to cause interaction between separate active regions. This interaction occurs by the penetration of charge carriers below one active region through the underlying substrate, across the substrate under the lateral isolation region, and up into the second active region. To prevent such undesirable electrical interaction between two active regions, vertical electrical isolation, in addition to lateral isolation, is employed. Vertical isolation is provided by underlying some, or most commonly all, of the single crystal silicon regions with a region of electrically insulating material. By this expedient, interaction between active regions even at high voltages is avoided.
Vertical isolation is also advantageously used in devices operating at nominal voltages where enhanced reliability is desirable. The additional insulating material that provides vertical isolation also prevents electron hole pairs formed in the underlying substrate by thermal processes or by ionizing radiation from migrating to an active region and, therefore, introducing errors in the processing of information by the electronic devices in this region. Additionally, the vertical isolation reduces capacitance and thus allows faster device operation.
Various processes have been employed to produce a component having both lateral and vertical isolation. For example, a dielectric isolation process is described by K. E. Bean and W. R. Runyan, in Journal of the Electrochemical Society, 124(1), 5C (1977). This process involves the use of a silicon substrate having a very low defect density. The silicon substrate is coated with an insulating material, such as silicon oxide, 3 in FIG. 1, and holes, 5, are formed in the oxide by conventional techniques, e.g., photolithography followed by chemical etching. Grooves, 7, are then etched in the exposed portions of the silicon underlying the holes in the dielectric material. Optionally, a region of N+ silicon, 8, is produced on grooves, 7. The N+ silicon is, in turn, coated with an insulator, 9, such as silicon oxide. The insulator is once again, in turn, coated with a layer of polycrystalline silicon, 10. The structure produced is denominated 1F in FIG. 1. The entire structure is then inverted; the silicon substrate is ground off until the structure shown at 1G is obtained. In this structure, the remaining high-quality silicon is denoted by 12, insulating layers are indicated by 14 and 15, and polycrystalline silicon is indicated by 16. Thus, the final structure has single crystal silicon, 12, on an electrically insulating material.
As the fabrication steps are performed in the process of FIG. 1, the substrate undergoes a variety of deformations. Generally, either (1) a bow, e.g., a concave or convex configuration, or (2) a ripple effect has been observed. Both deformations are not desirable. The former limits automated handling and affects yield during mechanical processing of DI substrates, while the latter substantially decreases yield due to stress-induced defects. For example, the growth of the polycrystalline silicon, exemplified by the addition of region, 10, from FIGS. 1E to 1F, has been reported to cause a substantial bow in the substrate, as shown in FIG. 2. (See T. Suzuki et al, Journal of the Electrochemical Society, 124, page 1776 (1977).) This bow has been ascribed to the substantial increase in the polycrystalline grain size resulting from the growth procedure. Ripple deformation, as exemplified in FIG. 3, has been observed when the configuration shown in FIG. 1G is subjected to an oxidizing atmosphere to produce device gate oxides in active region, 12.
To cure the defects associated with ripple deformations, the polycrystalline region, 16, of the substrate has been capped with a silicon nitride layer before formation of silicon oxide regions. (See U.S. Pat. No. 4,017,341, by T. Suzuki et al, issued Apr. 12, 1977, for a description of this procedure.) Capping with silicon nitride has, in fact, substantially reduced deformations of the FIG. 3 type but increases the bow deformation such as shown in FIG. 2. Additionally, use of a silicon nitride step requires both the deposition of silicon nitride and the ultimate removal of this layer to allow formation of electrical and thermal contacts.